Implemented block level physical design for a world’s largest OEM
One of the leading semiconductor companies based in USA
Project Scope
- Post-layout signal integrity analysis and post-layout timing analysis
- Test plan preparation for reliability testing
- Maintaining signal integrity for faster signal transmission
- Design and testing
Project Deliverables
- Static timing analysis using Prime
- Timing Eco flow SPEF generation by using Star RE-Extraction
- Reducing crosstalk in high-speed PCBs
Key Tools
- Synopsys version ICC2
- Synopsys' PrimeTime
- StarRC
- EDA
