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DFT Implementation and verification on 12nm for a leading OEM
Project Scope
The front-end team to fix the DFT DRC at the early stage of the design
DFT architecture for the design, including placing OCC, EDT, JTAG registers for SCAN, and MBIST mode controls
Core-wrapping blocks and using the comparator logic at the SoC level so that the same identity blocks can test simultaneously with a minimum number of output EDT channels
Deliverables
Post synthesis scan stitching, ATPG for all scan
Test integration and Re-targeted the sub blocks from the SoC level.
Generation and integration of ITAG TCR for SCAN and MBIST test mode control
Tools
TestMAX
ATPG
TCR
MBIST
Case Studies
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