Our Experienece
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Implemented block level physical design for a world’s largest OEM
Project Scope
- Post-layout signal integrity analysis and post-layout timing analysis
- Test plan preparation for reliability testing
- Maintaining signal integrity for faster signal transmission
- Design and testing
Deliverables
- Static timing analysis using Prime
- Timing Eco flow SPEF generation by using Star RE-Extraction
- Reducing crosstalk in high-speed PCBs
Tools
- Synopsys version ICC2
- Synopsys' PrimeTime
- StarRC
- EDA
Case Studies
We have provided a few projects which we have executd for our customers. Please reach out to us for more details